1. Field of the Invention
The present invention relates to a solid state imaging device, a method of manufacturing the same, and a solid state imaging system and, more particularly, a solid state imaging device using a MOS image sensor of a threshold voltage modulation system employed in a video camera, an electronic camera, an image input camera, a scanner, a facsimile, or the like, a method of manufacturing the same, and a solid state imaging system.
2. Description of the Prior Art
Since a semiconductor image sensor such as a CCD image sensor, a MOS image sensor, etc. is excellent in mass productivity, such semiconductor image sensor is applied to most of the image input devices with the progress of the fine pattern technology.
In particular, the MOS image sensor is reconsidered in recent years because of its merits that the power consumption is small rather than the CCD image sensor and that the sensor element and peripheral circuit elements can be fabricated by the same CMOS technology.
In view of the trend in the times, the applicant of this application has improved the MOS image sensor, and then secured the Patent (Registration Number 2935492) by filing the patent application (Patent Application Hei 10-186453) in connection with the image sensor device which has the carrier pocket (high concentration buried layer) under the channel region.
In the invention of this Patent (Registration Number 2935492), in order to suppress the injection of the light emitting charges into the surface defects of the semiconductor layer and thus reduce the noise, the photo diode has the buried structure for the light emitting charges (in this case, holes). More particularly, the n-type impurity region is formed on the surface layer of the p-type well region. This p-type well region is formed integrally with the p-type base region of the light signal detecting MOS transistor, and this n-type impurity region is formed integrally with the n-type drain region. As a result, the configuration can be formed in which the light emitting charges generated in the p-type well region of the photo diode portion can contribute to the detection of the light signal.
Meanwhile, in the MOS image sensor, normally the spectral sensitivity characteristic, especially the red-color sensitivity is low. Therefore, in order to broaden much more the applications of the MOS image sensor in the future, it is desired to achieve the improvement of the red-color sensitivity. In addition, it is desired to achieve the improvement of the blue-color sensitivity. At the same time, the higher integration degree of the solid state imaging device is also desired.
It is an object of the present invention to provide a solid state imaging device using a MOS image sensor capable of achieving improvement in red-color sensitivity and improvement in blue-color sensitivity while maintaining the performance of a light signal detecting MOS transistor, a method of manufacturing the same, and a solid state imaging system.
With reference to FIG. 2A, in order to improve the red-color sensitivity, it is desired that the n-type epitaxial layer (n-type layer) 12 on the p-type substrate 11 should be formed thicker than in the structure of applicants"" Patent Registration Number 2935492. However, if the n-type epitaxial layer (n-type layer) 12 is formed thicker, the reset voltage for the initialization to discharge the carriers must be increased and thus the performance of the light signal detecting MOS transistor is lowered. In other words, in order to improve the red-color sensitivity and to maintain/improve the reset efficiency, structures are needed which are incompatible with each other.
In the present invention, as exemplified by the embodiment shown in FIGS. 1 and 2A, in the store period during when the carriers are generated by the light in the photo diode 111 having the above structure and then stored in the high concentration buried layer (carrier pocket) 25 of opposite conductivity type, the depletion layer can spread from a boundary surface between the one conductivity type impurity region 17 and the opposite conductivity type first well region 15a in the photo diode 111 to the overall first well region 15a by the applied voltage. Further, the depletion layer can spread from a boundary surface between the opposite conductivity type substrate 11 and the one conductivity type buried layer 32 in the photo diode 111 to the first semiconductor layers 12 and 32. Therefore, the light emitting charges generated in the depleted first well region 15a and the first semiconductor layers 12 and 32 can contribute to the detection of the light signal.
In other words, since the thicknesses of the first semiconductor layers 12 and 32 are increased, the thickness of the light receiving region can be extended effectively with respect to the long wavelength light such as the red-color. Accordingly, the improvement of the red-color sensitivity can be achieved.
In contrast, in the sweep period (initialization period) during when the carriers are swept out from the high concentration buried layer 25 and the second well region 15b in the light signal detecting MOS transistor 112 portion, the depletion layer can spread from a boundary surface between the one conductivity type channel doped layer 15c and the opposite conductivity type second well region 15b into the second well region 15b by the applied voltage, and also the depletion layer can spread from a boundary surface between the opposite conductivity type sixth semiconductor layer 33 and the one conductivity type third semiconductor layer 12 into the third semiconductor layer 12 under the second well region 15b. 
As a result, the electric field from the gate electrode 19 can extend mainly to the depleted second well region 15b and the third semiconductor layer 12 formed under the second well region 15b. 
In the case of the present invention, the thickness of the third semiconductor layer 12 under the second well region 15b is small and the opposite conductivity type high concentration sixth semiconductor layer 33 is formed in the neighborhood of the one conductivity type third semiconductor layer 12 on the substrate 11 side. Therefore, extension of the depletion layer from the boundary surface between the opposite conductivity type sixth semiconductor layer 33 and the one conductivity type third semiconductor layer 12 into the sixth semiconductor layer 33 in the sweep period can be limited, and also the width of the depletion layer extending from the boundary surface to the third semiconductor layer 12 can be reduced. That is, the voltage from the gate electrode 19 is mainly applied to the second well region 15b. 
Accordingly, since the abrupt potential change that is fitted to sweep out the carriers is caused in the second well region 15b and thus the strong electric field is applied. Therefore, the stored carriers can be swept out effectively from the high concentration buried layer (carrier pocket) 25 and the second well region 15b by the low reset voltage, whereby the reset efficiency can be improved.
In addition, according to the present invention, since the low concentration drain (LDD) structure is employed as the structure of the light signal detecting MOS transistor 112, the short channel of the light signal detecting MOS transistor 112 can be achieved and thus the higher integration degree of the solid state imaging device can be achieved.
Also, the impurity region 117 is formed at the same time when the low concentration drain region 117a is formed. That is, since the impurity concentration of the impurity region 117 is set to the low concentration, the impurity region 117 can be formed at the shallow position from the surface. Accordingly, the blue-color that has the short wavelength and attenuates suddenly in the vicinity of the surface can be received at the sufficient intensity.
In addition, since the one conductivity type impurity region 17 is formed on the surface layer of the opposite conductivity type first well region 15a serving as the light receiving region, the photo diode 111 has the buried structure for the light emitting charges.
Accordingly, since the neutralized state against the trap level of the surface and the hole generation center can be maintained, the noise and the dark current due to the charges except the light emitting charge can be maintained low.
Accordingly, improvement of the blue-color sensitivity can be achieved while maintaining the noise and the dark current.
Also, the CMOS circuit for driving the solid state imaging device is formed on the same substrate as the solid state imaging device, and the low concentration impurity region 17 is formed at the same time when the low concentration drain region of the MOS transistor constituting the CMOS circuit and having the LDD structure is formed, and in addition the high concentration contact layer is formed at the same time when the high concentration drain region of the MOS transistor having the LDD structure is formed.
Accordingly, improvement of the blue sensitivity can be achieved while maintaining the noise and the dark current without increasing new manufacturing steps.
Correspondences between technical terms in the solid state imaging device manufacturing method and technical terms in the solid state imaging device are given as follows. That is, a part of the seventh semiconductor layers 11 and 31 corresponds to the first base layer, and a part of the seventh semiconductor layers 11 and 31 and the second buried layer 33 correspond to the second base layer (i.e., the substrate 11 and the sixth semiconductor layer). The first buried layer 32 corresponds to the buried layer or the fifth semiconductor layer, and the second buried layer 33 corresponds to the sixth semiconductor layer. The one conductivity type region 12 corresponds to the one conductivity type well region, and the first buried layer 32 and the one conductivity type region 12 correspond to the first semiconductor layer (i.e., the fifth semiconductor layer and the one conductivity type well region). The first well region 15a corresponds to the second semiconductor layer, and the one conductivity type region 12 corresponds to the one conductivity type third semiconductor layer (i.e., one conductivity type well region). The second well region corresponds to the fourth semiconductor layer.